1. Field of the Invention
The present invention relates in general to a bootstrap circuit for boosting a binary signal of specified logic, and more particularly to an improved bootstrap circuit for adjusting an output load amount according to a variation of a supply voltage to boost the binary signal to a desired voltage level.
2. Description of the Prior Art
Generally, a bootstrap circuit functions, such as a typical amplifier, to boost an input signal. In practice, the bootstrap circuit boosts a binary signal to be supplied to a word line of a semiconductor memory device and a pull-up driver of a data output buffer thereof consisting of NMOS transistors, so as to enhance an operation speed and a reliability of the semiconductor memory device.
Such a conventional bootstrap circuit has a fixed amount of output load and a constant boosting efficiency due to the fixed output load amount. For this reason, when a supply voltage is varied, the conventional bootstrap circuit generates an output signal with a boosted voltage level varied with the variation of the supply voltage. The variation of the boosted voltage level degrades the operation speed and the reliability of the semiconductor memory device. Such a problem with the conventional bootstrap circuit will hereinafter be described with reference to FIGS. 1 and 2.
Referring to FIG. 1, there is shown a circuit diagram of the conventional bootstrap circuit for the data output buffer of the semiconductor memory device which is designated by the reference numeral 3. As shown in this drawing, the conventional bootstrap circuit comprises a booster 1 for boosting a data signal from a node N0 and a voltage compensator 2 for compensating for a voltage loss of the data signal boosted by the booster 1.
The booster 1 is adapted to boost the data signal from the node N0 and supply the boosted data signal through a node N5 to a gate of an NMOS transistor Q3 of the data output buffer 3. To this end, the booster 1 includes two NMOS transistors Q1 and Q2, six inverters G1-G6 and a capacitor CAP1. The operation of the booster 1 with the above-mentioned construction will hereinafter be described.
First, in the case where the data signal at the node N0 is high in logic, a low logic signal is generated at a node N1 by the inverter G1. A high logic signal is generated at a node N2 after the lapse of a first predetermined time period from the application of the high data signal to the node N0. A voltage of "Vcc-Vt" is maintained at a node N3 by the NMOS transistor Q2, where Vcc is a first supply voltage from a first supply voltage source Vcc and Vt is a threshold voltage of the NMOS transistor Q2. The first predetermined time period corresponds to the sum of propagation delay times of the two inverters G2 and G3 connected in series between the nodes N0 and N2. As the NMOS transistor Q1 is turned on by the voltage Vcc-Vt at the node N3, the same low logic signal as that at the node N1 is maintained at the node N5. A low logic signal is maintained at a node N4 after the lapse of the first predetermined time period from the application of the high data signal to the node N0. With the low logic signals maintained at the nodes N4 and N5, a voltage of 0 V from the capacitor CAP1 is transferred through the node N5 to the gate of the NMOS transistor Q3 of the data output buffer 3.
On the other hand, in the case where the data signal at the node N0 is transited from its high logic to its low logic, the logic signal at the node N1 is changed from its low level to its high level by the inverter G1. The voltage Vcc-Vt at the node N3 is boosted to at least "Vcc+2Vt" under the influence of a parasitic capacitor which is present between a source and a gate of the NMOS transistor Q1. The boosted voltage Vcc+2Vt at the node N3 causes the NMOS transistor Q1 to transfer the high logic signal at the node N1 to the node N5 with no loss, so as to charge the capacitor CAP1.
After the lapse of the first predetermined time period from the moment that the data signal at the node N0 is transited from its high logic to its low logic, a low state is maintained at the node N2 by the delayed data signal from the inverter G3, thereby causing the NMOS transistor Q2 to be turned off. With the NMOS transistor Q2 turned off, the node N5 is floated at a high state. After the lapse of a second predetermined time period from the moment that the data signal at the node N0 is transited from its high logic to its low logic, a high state is maintained at the node N4 by a logic signal from the inverter G6, thereby causing a voltage at the node N5 to be boosted to at least "Vcc+3Vt". The boosted voltage at the node N5 is applied to the gate of the NMOS transistor Q3 of the data output buffer 3.
The voltage compensator 2 is adapted to input a pulse signal from a ring oscillator (not shown) through a node N6 and supply periodically a voltage to the node N5 in response to the inputted pulse signal, to make up for the voltage loss caused with the lapse of time. To this end, the voltage compensator 2 includes a capacitor CAP2 and three NMOS transistors Q5-A7, as shown in FIG. 2.
In FIG. 2, the NMOS transistor Q7 is turned on when the voltage at the node N5 is about "Vcc+3Vt", thereby causing the first supply voltage from the first supply voltage source Vcc to be transferred to a node N7 through the NMOS transistor Q6, which acts as a resistor. When the pulse signal applied through the node N6 from the ring oscillator (not shown) remains at its high logic, the voltage at the node N7 is boosted to at least "Vcc+3Vt" by the capacitor CAP2. Then, the boosted voltage Vcc+3Vt at the node N7 is transferred to the node N5 by the NMOS transistor Q5, so as to compensate for the voltage loss at the capacitor CAP1 in FIG. 1. At this time, the capacitor CAP1 is charged with the voltage from the NMOS transistor Q5.
However, the above-mentioned conventional bootstrap circuit has the disadvantage that the data signal is boosted to an exceedingly high voltage level when the supply voltage is high, because the boosting efficiency is constant regardless of the variation of the supply voltage. For this reason, the conventional bootstrap circuit degrades the operation speed of the data output buffer and, thus, the reliability of the semiconductor memory device.